1. Field
This disclosure relates generally to data processing systems, and more specifically, to a data processing system with a cache linefill buffer.
2. Related Art
Cache memories are typically used within data processing systems in order to reduce memory access times. Caches are smaller, faster memories used to store copies of data which reside in the slower memory. Since caches are typically much faster to access than the memory, it is desirable to store data which resides at more frequently accessed memory locations within the cache. If a read memory access request (i.e. a load access request) is made to a cache, and the access address of the read access request is stored in the cache, a cache hit occurs and the read data can be provided from the cache rather than having to access the slower memory. This prevents the extra latency introduced from having to access the slower memory to respond to the access request. However, if the read memory access request is not stored in the cache, a cache miss occurs and the read request is made to the memory to retrieve the read data. The read data can also be stored into the cache so that, if subsequently accessed, a cache hit will occur. Furthermore, in an attempt to improve the rate of cache hits, the read request to the memory can be provided as a burst request in order to obtain a full cache line of data rather than just the specifically requested data. A linefill buffer may be used to collect the data received in response to the burst request prior to updating the cache with the data. In this manner, a full cache line can be collected prior to updating the cache.
In many data processing systems, external memories are capable of handling multiple outstanding access requests and can provide read data in response to these access requests out of order. While additional linefill buffers may be used to collect cache line data for different cache lines, additional linefill buffers result in increased circuit area which is undesirable. Therefore, a need exists for a cache controller which is capable of handling multiple outstanding access requests, with either in or out of order return data, without expanding the number of linefill buffers.